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Methodology for Active Junction Profile Extraction in thin film FD-SOI Enabling performance driver identification in 500°C devices for 3D sequential integration

Tadeu Mota Frutuoso, Xavier Garros, Perrine Batude, Laurent Brunet, Joris Lacord, B. Sklenard, V. Lapras, Claire Fenouillet-Béranger, M. Ribotta, A. Magalhaes-Lucas, J. Kanyandekwe, R. Kies, G. Romano, Edoardo Catapano, Mikaël Cassé, Jose Lugo-Alvarez, P. Ferrari, Fred Gaillard. Methodology for Active Junction Profile Extraction in thin film FD-SOI Enabling performance driver identification in 500°C devices for 3D sequential integration. In IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), Honolulu, HI, USA, June 12-17, 2022. pages 332-333, IEEE, 2022. [doi]

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Tadeu Mota Frutuoso

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Xavier Garros

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Perrine Batude

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Laurent Brunet

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Joris Lacord

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B. Sklenard

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V. Lapras

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Claire Fenouillet-Béranger

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M. Ribotta

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A. Magalhaes-Lucas

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J. Kanyandekwe

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R. Kies

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G. Romano

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Edoardo Catapano

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Mikaël Cassé

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Jose Lugo-Alvarez

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P. Ferrari

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Fred Gaillard

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