Chen Fu, Dongxin Wen, Xiaoqun Wang, Xiao-Zong Yang. Hardware transactional memory: A high performance parallel programming model. Journal of Systems Architecture, 56(8):384-391, 2010. [doi]
@article{FuWWY10,
title = {Hardware transactional memory: A high performance parallel programming model},
author = {Chen Fu and Dongxin Wen and Xiaoqun Wang and Xiao-Zong Yang},
year = {2010},
doi = {10.1016/j.sysarc.2010.06.006},
url = {http://dx.doi.org/10.1016/j.sysarc.2010.06.006},
tags = {parallel programming, programming},
researchr = {https://researchr.org/publication/FuWWY10},
cites = {0},
citedby = {0},
journal = {Journal of Systems Architecture},
volume = {56},
number = {8},
pages = {384-391},
}