Design Automation Methodology from RTL to Gate-level Netlist and Schematic for RSFQ Logic Circuits - researchr publication authors

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Rongliang Fu, Zhimin Zhang, Guang-Ming Tang, Junying Huang, Xiaochun Ye, Dongrui Fan, Ninghui Sun. Design Automation Methodology from RTL to Gate-level Netlist and Schematic for RSFQ Logic Circuits. In Tinoosh Mohsenin, Weisheng Zhao, Yiran Chen, Onur Mutlu, editors, GLSVLSI '20: Great Lakes Symposium on VLSI 2020, Virtual Event, China, September 7-9, 2020. pages 145-150, ACM, 2020. [doi]

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