How to Speed-Up Fault-Tolerant Clock Generation in VLSI Systems-on-Chip via Pipelining - researchr publication

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Matthias Függer, Andreas Dielacher, Ulrich Schmid. How to Speed-Up Fault-Tolerant Clock Generation in VLSI Systems-on-Chip via Pipelining. In Eighth European Dependable Computing Conference, EDCC-8 2010, Valencia, Spain,28-30 April 2010. pages 230-239, IEEE Computer Society, 2010. [doi]

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