Logic synthesis and verification on fixed topology - researchr publication authors

researchr

You are not signed in
Sign in
Sign up

Masahiro Fujita, Alan Mishchenko. Logic synthesis and verification on fixed topology. In Lorena Garcia, editor, 22nd International Conference on Very Large Scale Integration, VLSI-SoC, Playa del Carmen, Mexico, October 6-8, 2014. pages 1-6, IEEE, 2014. [doi]

This author has not been identified. Look up 'Masahiro Fujita' in GoogleThis author has not been identified. Look up 'Alan Mishchenko' in Google

runs on WebDSL