Shinobu Fujita, Hiroki Noguchi, Kazutaka Ikegami, Susumu Takeda, Kumiko Nomura, Keiko Abe. Novel STT-MRAM-based last level caches for high performance processors using normally-off architectures. In 2014 International Symposium on Integrated Circuits (ISIC), Singapore, December 10-12, 2014. pages 316-319, IEEE, 2014. [doi]
Abstract is missing.