Koichi Fujiwara, Shin-ya Abe, Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa. A floorplan-aware high-level synthesis algorithm for multiplexer reduction targeting FPGA designs. In 2014 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2014, Ishigaki, Japan, November 17-20, 2014. pages 244-247, IEEE, 2014. [doi]
Abstract is missing.