Hidehiro Fujiwara, Chih-Yu Lin, Hsien-Yu Pan, Cheng-Han Lin, Po-Yi Huang, Kao-Cheng Lin, Jhon-Jhy Liaw, Yen-Huei Chen, Hung-Jen Liao, Jonathan Chang. A 7nm 2.1GHz Dual-Port SRAM with WL-RC Optimization and Dummy-Read-Recovery Circuitry to Mitigate Read- Disturb-Write Issue. In IEEE International Solid- State Circuits Conference, ISSCC 2019, San Francisco, CA, USA, February 17-21, 2019. pages 390-392, IEEE, 2019. [doi]
@inproceedings{FujiwaraLPLHLLC19,
title = {A 7nm 2.1GHz Dual-Port SRAM with WL-RC Optimization and Dummy-Read-Recovery Circuitry to Mitigate Read- Disturb-Write Issue},
author = {Hidehiro Fujiwara and Chih-Yu Lin and Hsien-Yu Pan and Cheng-Han Lin and Po-Yi Huang and Kao-Cheng Lin and Jhon-Jhy Liaw and Yen-Huei Chen and Hung-Jen Liao and Jonathan Chang},
year = {2019},
doi = {10.1109/ISSCC.2019.8662415},
url = {https://doi.org/10.1109/ISSCC.2019.8662415},
researchr = {https://researchr.org/publication/FujiwaraLPLHLLC19},
cites = {0},
citedby = {0},
pages = {390-392},
booktitle = {IEEE International Solid- State Circuits Conference, ISSCC 2019, San Francisco, CA, USA, February 17-21, 2019},
publisher = {IEEE},
isbn = {978-1-5386-8531-0},
}