HLS Implementation of a Building Cube Stencil Computation Framework for an FPGA Accelerator

Daiki Furukawa, Taito Manabe, Yuichiro Shibata, Tomohiro Ueno, Kentaro Sano. HLS Implementation of a Building Cube Stencil Computation Framework for an FPGA Accelerator. In IEEE International Conference on Consumer Electronics, ICCE 2024, Las Vegas, NV, USA, January 6-8, 2024. pages 1-6, IEEE, 2024. [doi]

Abstract

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