CPU Architecture Based on a Hardware Scheduler and Independent Pipeline Registers

Vasile Gheorghita Gaitan, Nicoleta-Cristina Gaitan, Ioan Ungurean. CPU Architecture Based on a Hardware Scheduler and Independent Pipeline Registers. IEEE Trans. VLSI Syst., 23(9):1661-1674, 2015. [doi]

@article{GaitanGU15,
  title = {CPU Architecture Based on a Hardware Scheduler and Independent Pipeline Registers},
  author = {Vasile Gheorghita Gaitan and Nicoleta-Cristina Gaitan and Ioan Ungurean},
  year = {2015},
  doi = {10.1109/TVLSI.2014.2346542},
  url = {http://dx.doi.org/10.1109/TVLSI.2014.2346542},
  researchr = {https://researchr.org/publication/GaitanGU15},
  cites = {0},
  citedby = {0},
  journal = {IEEE Trans. VLSI Syst.},
  volume = {23},
  number = {9},
  pages = {1661-1674},
}