Xiang Gao, Olivier Burg, Haisong Wang, Wanghua Wu, Cao-Thong Tu, Konstantinos Manetakis, Fan Zhang, Luns Tee, Mustafa Yayla, Sining Xiang, Randy Tsang, Li Lin. 9.6 A 2.7-to-4.3GHz, 0.16psrms-jitter, -246.8dB-FOM, digital fractional-N sampling PLL in 28nm CMOS. In 2016 IEEE International Solid-State Circuits Conference, ISSCC 2016, San Francisco, CA, USA, January 31 - February 4, 2016. pages 174-175, IEEE, 2016. [doi]
@inproceedings{GaoBWWTMZTYXTL16,
title = {9.6 A 2.7-to-4.3GHz, 0.16psrms-jitter, -246.8dB-FOM, digital fractional-N sampling PLL in 28nm CMOS},
author = {Xiang Gao and Olivier Burg and Haisong Wang and Wanghua Wu and Cao-Thong Tu and Konstantinos Manetakis and Fan Zhang and Luns Tee and Mustafa Yayla and Sining Xiang and Randy Tsang and Li Lin},
year = {2016},
doi = {10.1109/ISSCC.2016.7417963},
url = {http://dx.doi.org/10.1109/ISSCC.2016.7417963},
researchr = {https://researchr.org/publication/GaoBWWTMZTYXTL16},
cites = {0},
citedby = {0},
pages = {174-175},
booktitle = {2016 IEEE International Solid-State Circuits Conference, ISSCC 2016, San Francisco, CA, USA, January 31 - February 4, 2016},
publisher = {IEEE},
isbn = {978-1-4673-9467-3},
}