Zhong Gao, Jingchu He, Martin Fritz, Jiang Gong, Yiyu Shen, Zhirui Zong, Peng Chen 0022, Gerd Spalink, Ben Eitel, Ken Yamamoto, Robert Bogdan Staszewski, Morteza S. Alavi, Masoud Babaie. A 2.6-to-4.1GHz Fractional-N Digital PLL Based on a Time-Mode Arithmetic Unit Achieving -249.4dB FoM and -59dBc Fractional Spurs. In IEEE International Solid-State Circuits Conference, ISSCC 2022, San Francisco, CA, USA, February 20-26, 2022. pages 380-382, IEEE, 2022. [doi]
@inproceedings{GaoHFGSZ0SEYSAB22,
title = {A 2.6-to-4.1GHz Fractional-N Digital PLL Based on a Time-Mode Arithmetic Unit Achieving -249.4dB FoM and -59dBc Fractional Spurs},
author = {Zhong Gao and Jingchu He and Martin Fritz and Jiang Gong and Yiyu Shen and Zhirui Zong and Peng Chen 0022 and Gerd Spalink and Ben Eitel and Ken Yamamoto and Robert Bogdan Staszewski and Morteza S. Alavi and Masoud Babaie},
year = {2022},
doi = {10.1109/ISSCC42614.2022.9731561},
url = {https://doi.org/10.1109/ISSCC42614.2022.9731561},
researchr = {https://researchr.org/publication/GaoHFGSZ0SEYSAB22},
cites = {0},
citedby = {0},
pages = {380-382},
booktitle = {IEEE International Solid-State Circuits Conference, ISSCC 2022, San Francisco, CA, USA, February 20-26, 2022},
publisher = {IEEE},
isbn = {978-1-6654-2800-2},
}