On error modeling of electrical bugs for post-silicon timing validation - researchr publication authors

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Ming Gao, Peter Lisherness, Kwang-Ting Cheng, Jing-Jia Liou. On error modeling of electrical bugs for post-silicon timing validation. In Proceedings of the 17th Asia and South Pacific Design Automation Conference, ASP-DAC 2012, Sydney, Australia, January 30 - February 2, 2012. pages 701-706, IEEE, 2012. [doi]

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