Ming Gao, Peter Lisherness, Kwang-Ting Cheng, Jing-Jia Liou. On error modeling of electrical bugs for post-silicon timing validation. In Proceedings of the 17th Asia and South Pacific Design Automation Conference, ASP-DAC 2012, Sydney, Australia, January 30 - February 2, 2012. pages 701-706, IEEE, 2012. [doi]
@inproceedings{GaoLCL12,
title = {On error modeling of electrical bugs for post-silicon timing validation},
author = {Ming Gao and Peter Lisherness and Kwang-Ting Cheng and Jing-Jia Liou},
year = {2012},
doi = {10.1109/ASPDAC.2012.6165046},
url = {http://dx.doi.org/10.1109/ASPDAC.2012.6165046},
researchr = {https://researchr.org/publication/GaoLCL12},
cites = {0},
citedby = {0},
pages = {701-706},
booktitle = {Proceedings of the 17th Asia and South Pacific Design Automation Conference, ASP-DAC 2012, Sydney, Australia, January 30 - February 2, 2012},
publisher = {IEEE},
isbn = {978-1-4673-0770-3},
}