Vinay Gautam, Kailash Chandra Ray, Pauline Haddow. Hardware efficient design of Variable Length FFT Processor. In Rolf Kraemer, Adam Pawlak, Andreas Steininger, Mario Schölzel, Jaan Raik, Heinrich Theodor Vierhaus, editors, 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2011, Cottbus, Germany, April 13-15, 2011. pages 309-312, IEEE, 2011. [doi]
@inproceedings{GautamRH11,
title = {Hardware efficient design of Variable Length FFT Processor},
author = {Vinay Gautam and Kailash Chandra Ray and Pauline Haddow},
year = {2011},
doi = {10.1109/DDECS.2011.5783102},
url = {http://dx.doi.org/10.1109/DDECS.2011.5783102},
researchr = {https://researchr.org/publication/GautamRH11},
cites = {0},
citedby = {0},
pages = {309-312},
booktitle = {14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2011, Cottbus, Germany, April 13-15, 2011},
editor = {Rolf Kraemer and Adam Pawlak and Andreas Steininger and Mario Schölzel and Jaan Raik and Heinrich Theodor Vierhaus},
publisher = {IEEE},
isbn = {978-1-4244-9755-3},
}