Michael Gautschi, Michael Schaffner, Frank K. Gürkaynak, Luca Benini. 4.6 A 65nm CMOS 6.4-to-29.2pJ/FLOP@0.8V shared logarithmic floating point unit for acceleration of nonlinear function kernels in a tightly coupled processor cluster. In 2016 IEEE International Solid-State Circuits Conference, ISSCC 2016, San Francisco, CA, USA, January 31 - February 4, 2016. pages 82-83, IEEE, 2016. [doi]
@inproceedings{GautschiSGB16,
title = {4.6 A 65nm CMOS 6.4-to-29.2pJ/FLOP@0.8V shared logarithmic floating point unit for acceleration of nonlinear function kernels in a tightly coupled processor cluster},
author = {Michael Gautschi and Michael Schaffner and Frank K. Gürkaynak and Luca Benini},
year = {2016},
doi = {10.1109/ISSCC.2016.7417917},
url = {http://dx.doi.org/10.1109/ISSCC.2016.7417917},
researchr = {https://researchr.org/publication/GautschiSGB16},
cites = {0},
citedby = {0},
pages = {82-83},
booktitle = {2016 IEEE International Solid-State Circuits Conference, ISSCC 2016, San Francisco, CA, USA, January 31 - February 4, 2016},
publisher = {IEEE},
isbn = {978-1-4673-9467-3},
}