Ultra-low power and high speed design and implementation of AES and SHA1 hardware cores in 65 nanometer CMOS technology - researchr publication authors

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Feng Ge, P. Jain, Ken Choi. Ultra-low power and high speed design and implementation of AES and SHA1 hardware cores in 65 nanometer CMOS technology. In 2009 IEEE International Conference on Electro/Information Technology, EIT 2009, Windsor, Ontario, Canada, June 7-9, 2009. pages 405-410, IEEE, 2009. [doi]

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