Chao Geng, Bo Liu, Shigetoshi Nakatake. Density Optimization for Analog Layout Based on Transistor-Array. IEICE Transactions, 102-A(12):1720-1730, 2019. [doi]
@article{GengLN19,
title = {Density Optimization for Analog Layout Based on Transistor-Array},
author = {Chao Geng and Bo Liu and Shigetoshi Nakatake},
year = {2019},
url = {http://search.ieice.org/bin/summary.php?id=e102-a_12_1720},
researchr = {https://researchr.org/publication/GengLN19},
cites = {0},
citedby = {0},
journal = {IEICE Transactions},
volume = {102-A},
number = {12},
pages = {1720-1730},
}