Santosh Ghosh, Avishek Saha. Speed-area optimized FPGA implementation for Full Search Block Matching. In 25th International Conference on Computer Design, ICCD 2007, 7-10 October 2007, Lake Tahoe, CA, USA, Proceedings. pages 13-18, IEEE, 2007. [doi]
@inproceedings{GhoshS07:1,
title = {Speed-area optimized FPGA implementation for Full Search Block Matching},
author = {Santosh Ghosh and Avishek Saha},
year = {2007},
doi = {10.1109/ICCD.2007.4601874},
url = {http://dx.doi.org/10.1109/ICCD.2007.4601874},
tags = {optimization, search},
researchr = {https://researchr.org/publication/GhoshS07%3A1},
cites = {0},
citedby = {0},
pages = {13-18},
booktitle = {25th International Conference on Computer Design, ICCD 2007, 7-10 October 2007, Lake Tahoe, CA, USA, Proceedings},
publisher = {IEEE},
isbn = {1-4244-1258-7},
}