An 820μW 9b 40MS/s Noise-Tolerant Dynamic-SAR ADC in 90nm Digital CMOS

Vito Giannini, Pierluigi Nuzzo, Vincenzo Chironi, Andrea Baschirotto, Geert Van der Plas, Jan Craninckx. An 820μW 9b 40MS/s Noise-Tolerant Dynamic-SAR ADC in 90nm Digital CMOS. In 2008 IEEE International Solid-State Circuits Conference, ISSCC 2008, Digest of Technical Papers, San Francisco, CA, USA, February 3-7, 2008. pages 238-239, IEEE, 2008. [doi]

@inproceedings{GianniniNCBPC08,
  title = {An 820μW 9b 40MS/s Noise-Tolerant Dynamic-SAR ADC in 90nm Digital CMOS},
  author = {Vito Giannini and Pierluigi Nuzzo and Vincenzo Chironi and Andrea Baschirotto and Geert Van der Plas and Jan Craninckx},
  year = {2008},
  doi = {10.1109/ISSCC.2008.4523145},
  url = {http://dx.doi.org/10.1109/ISSCC.2008.4523145},
  researchr = {https://researchr.org/publication/GianniniNCBPC08},
  cites = {0},
  citedby = {0},
  pages = {238-239},
  booktitle = {2008 IEEE International Solid-State Circuits Conference, ISSCC 2008, Digest of Technical Papers, San Francisco, CA, USA, February 3-7, 2008},
  publisher = {IEEE},
  isbn = {978-1-4244-2010-0},
}