V. S. Gierenz, Oliver Weiss, Tobias G. Noll, I. Carew, J. Ashley, R. Karabed. A 550 Mb/s Radix-4 Bit-level Pipelined 16-State 0.25-mu m CMOS Viterbi Decoder. In 12th IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP 2000), 10-12 July 2000, Boston, MA, USA. pages 195, IEEE Computer Society, 2000. [doi]
@inproceedings{GierenzWNCAK00,
title = {A 550 Mb/s Radix-4 Bit-level Pipelined 16-State 0.25-mu m CMOS Viterbi Decoder},
author = {V. S. Gierenz and Oliver Weiss and Tobias G. Noll and I. Carew and J. Ashley and R. Karabed},
year = {2000},
doi = {10.1109/ASAP.2000.862390},
url = {http://doi.ieeecomputersociety.org/10.1109/ASAP.2000.862390},
researchr = {https://researchr.org/publication/GierenzWNCAK00},
cites = {0},
citedby = {0},
pages = {195},
booktitle = {12th IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP 2000), 10-12 July 2000, Boston, MA, USA},
publisher = {IEEE Computer Society},
isbn = {0-7695-0716-6},
}