A compact 14-bit 110 KS/s two-stage incremental ΣΔ ADC for CMOS image sensors

Francesco Giorgio, Bhaskar Choubey. A compact 14-bit 110 KS/s two-stage incremental ΣΔ ADC for CMOS image sensors. In IEEE 60th International Midwest Symposium on Circuits and Systems, MWSCAS 2017, Boston, MA, USA, August 6-9, 2017. pages 1180-1183, IEEE, 2017. [doi]

@inproceedings{GiorgioC17,
  title = {A compact 14-bit 110 KS/s two-stage incremental ΣΔ ADC for CMOS image sensors},
  author = {Francesco Giorgio and Bhaskar Choubey},
  year = {2017},
  doi = {10.1109/MWSCAS.2017.8053139},
  url = {https://doi.org/10.1109/MWSCAS.2017.8053139},
  researchr = {https://researchr.org/publication/GiorgioC17},
  cites = {0},
  citedby = {0},
  pages = {1180-1183},
  booktitle = {IEEE 60th International Midwest Symposium on Circuits and Systems, MWSCAS 2017, Boston, MA, USA, August 6-9, 2017},
  publisher = {IEEE},
  isbn = {978-1-5090-6389-5},
}