Testing CMOS combinational iterative logic arrays for realistic faults

Dimitris Gizopoulos, Dimitris Nikolos, Antonis M. Paschalis. Testing CMOS combinational iterative logic arrays for realistic faults. Integration, 21(3):209-228, 1996. [doi]

@article{GizopoulosNP96,
  title = {Testing CMOS combinational iterative logic arrays for realistic faults},
  author = {Dimitris Gizopoulos and Dimitris Nikolos and Antonis M. Paschalis},
  year = {1996},
  doi = {10.1016/S0167-9260(96)00000-4},
  url = {http://dx.doi.org/10.1016/S0167-9260(96)00000-4},
  tags = {testing, logic},
  researchr = {https://researchr.org/publication/GizopoulosNP96},
  cites = {0},
  citedby = {0},
  journal = {Integration},
  volume = {21},
  number = {3},
  pages = {209-228},
}