Retiming arithmetic datapaths using Timed Taylor Expansion Diagrams

Daniel Gomez-Prado, Dusung Kim, Maciej J. Ciesielski, Emmanuel Boutillon. Retiming arithmetic datapaths using Timed Taylor Expansion Diagrams. In IEEE International High Level Design Validation and Test Workshop, HLDVT 2010, Anaheim, CA, USA, 10-12 June 2010. pages 33-39, IEEE, 2010. [doi]

Authors

Daniel Gomez-Prado

This author has not been identified. Look up 'Daniel Gomez-Prado' in Google

Dusung Kim

This author has not been identified. Look up 'Dusung Kim' in Google

Maciej J. Ciesielski

This author has not been identified. Look up 'Maciej J. Ciesielski' in Google

Emmanuel Boutillon

This author has not been identified. Look up 'Emmanuel Boutillon' in Google