Compact Signed-Digit Adder Using Multiple-Valued Logic

Alejandro F. González, Pinaki Mazumder. Compact Signed-Digit Adder Using Multiple-Valued Logic. In 17th Conference on Advanced Research in VLSI (ARVLSI 97), September 15-16, 1997, Ann Arbor, MI, USA. pages 96-113, IEEE Computer Society, 1997. [doi]

@inproceedings{GonzalezM97,
  title = {Compact Signed-Digit Adder Using Multiple-Valued Logic},
  author = {Alejandro F. González and Pinaki Mazumder},
  year = {1997},
  doi = {10.1109/ARVLSI.1997.634849},
  url = {http://doi.ieeecomputersociety.org/10.1109/ARVLSI.1997.634849},
  tags = {logic},
  researchr = {https://researchr.org/publication/GonzalezM97},
  cites = {0},
  citedby = {0},
  pages = {96-113},
  booktitle = {17th Conference on Advanced Research in VLSI (ARVLSI  97), September 15-16, 1997, Ann Arbor, MI, USA},
  publisher = {IEEE Computer Society},
}