A Spatial Multi-Bit Sub-1-V Time-Domain Matrix Multiplier Interface for Approximate Computing in 65-nm CMOS - researchr publication

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Srinivasan Gopal, Pawan Agarwal, Joe Baylon, Luke Renaud, Sheikh Nijam Ali, Partha Pratim Pande, Deukhyoun Heo. A Spatial Multi-Bit Sub-1-V Time-Domain Matrix Multiplier Interface for Approximate Computing in 65-nm CMOS. IEEE J. Emerg. Sel. Topics Circuits Syst., 8(3):506-518, 2018. [doi]

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