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Achieving near-MLD performance with soft information-set decoders implemented in FPGAs

Antonio Gortan, Ricardo P. Jasinski, Walter Godoy Jr., Volnei A. Pedroni. Achieving near-MLD performance with soft information-set decoders implemented in FPGAs. In 2012 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2010, Kuala Lumpur, Malaysia, December 6-9, 2010. pages 312-315, IEEE, 2010. [doi]

Authors

Antonio Gortan

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Ricardo P. Jasinski

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Walter Godoy Jr.

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Volnei A. Pedroni

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