Orna Grumberg, Assaf Schuster, Avi Yadgar. 3-Valued Circuit SAT for STE with Automatic Refinement. In Kedar S. Namjoshi, Tomohiro Yoneda, Teruo Higashino, Yoshio Okamura, editors, Automated Technology for Verification and Analysis, 5th International Symposium, ATVA 2007, Tokyo, Japan, October 22-25, 2007, Proceedings. Volume 4762 of Lecture Notes in Computer Science, pages 457-473, Springer, 2007. [doi]
Abstract is missing.