Mahendrakumar Gunasekaran, Kumar Rahul, Santosh Yachareni. Optimizing Sub bytes and Mix Column to improve performance of AES in Virtex 7 FPGA. In International Symposium on Networks, Computers and Communications, ISNCC 2021, Dubai, United Arab Emirates, October 31 - November 2, 2021. pages 1-5, IEEE, 2021. [doi]
Abstract is missing.