Algorithm/Hardware Co-Design Configurable SAR ADC with Low Power for Computing-in-Memory in 28nm CMOS - researchr publication

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Zhiwang Guo, Deyang Chen, Xiaoyong Xue. Algorithm/Hardware Co-Design Configurable SAR ADC with Low Power for Computing-in-Memory in 28nm CMOS. In Fan Ye, Ting-Ao Tang, editors, 14th IEEE International Conference on ASIC, ASICON 2021, Kunming, China, October 26-29, 2021. pages 1-4, IEEE, 2021. [doi]

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