Ruiqi Guo, Zhiheng Yue, Xin Si, Te Hu, Hao Li, Limei Tang, Yabing Wang, Leibo Liu, Meng-Fan Chang, Qiang Li, Shaojun Wei, Shouyi Yin. 15.4 A 5.99-to-691.1TOPS/W Tensor-Train In-Memory-Computing Processor Using Bit-Level-Sparsity-Based Optimization and Variable-Precision Quantization. In IEEE International Solid-State Circuits Conference, ISSCC 2021, San Francisco, CA, USA, February 13-22, 2021. pages 242-244, IEEE, 2021. [doi]
@inproceedings{GuoYSHLTWLCLWY21,
title = {15.4 A 5.99-to-691.1TOPS/W Tensor-Train In-Memory-Computing Processor Using Bit-Level-Sparsity-Based Optimization and Variable-Precision Quantization},
author = {Ruiqi Guo and Zhiheng Yue and Xin Si and Te Hu and Hao Li and Limei Tang and Yabing Wang and Leibo Liu and Meng-Fan Chang and Qiang Li and Shaojun Wei and Shouyi Yin},
year = {2021},
doi = {10.1109/ISSCC42613.2021.9365989},
url = {https://doi.org/10.1109/ISSCC42613.2021.9365989},
researchr = {https://researchr.org/publication/GuoYSHLTWLCLWY21},
cites = {0},
citedby = {0},
pages = {242-244},
booktitle = {IEEE International Solid-State Circuits Conference, ISSCC 2021, San Francisco, CA, USA, February 13-22, 2021},
publisher = {IEEE},
isbn = {978-1-7281-9549-0},
}