Low Power Probabilistic Floating Point Multiplier Design - researchr publication authors

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Aman Gupta, Satyam Mandavalli, Vincent J. Mooney, Keck Voon Ling, Arindam Basu, Henry Johan, Budianto Tandianus. Low Power Probabilistic Floating Point Multiplier Design. In IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2011, 4-6 July 2011, Chennai, India. pages 182-187, IEEE Computer Society, 2011. [doi]

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