A 2 Gb/s balanced AES crypto-chip implementation - researchr publication authors

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Frank K. Gürkaynak, Andreas Burg, Norbert Felber, Wolfgang Fichtner, D. Gasser, F. Hug, Hubert Kaeslin. A 2 Gb/s balanced AES crypto-chip implementation. In David Garrett, John Lach, Charles A. Zukowski, editors, Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, Boston, MA, USA, April 26-28, 2004. pages 39-44, ACM, 2004. [doi]

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