A 7.5Gb/s/pin LPDDR5 SDRAM With WCK Clocking and Non-Target ODT for High Speed and With DVFS, Internal Data Copy, and Deep-Sleep Mode for Low Power

Kyung-Soo Ha, Chang-Kyo Lee, Dongkeon Lee, Daesik Moon, Jin-Hun Jang, Hyong-Ryol Hwang, Hyung-Joon Chi, Junghwan Park, Seungjun Shin, Dukha Park, Sang Yun Kim, Sukhyun Lim, Kiwon Park, YeonKyu Choi, Young-Hwa Kim, Younghoon Son, Hyunyoon Cho, Byongwook Na, Hyo-Joo Ahn, SeungSeob Lee, Seouk-Kyu Choi, Youn-Sik Park, Seok-Hun Hyun, Soobong Chang, Hyuck-Joon Kwon, Jung Hwan Choi, Tae-young Oh, Young-Soo Sohn, Kwang-Il Park, Seong-Jin Jang. A 7.5Gb/s/pin LPDDR5 SDRAM With WCK Clocking and Non-Target ODT for High Speed and With DVFS, Internal Data Copy, and Deep-Sleep Mode for Low Power. In IEEE International Solid- State Circuits Conference, ISSCC 2019, San Francisco, CA, USA, February 17-21, 2019. pages 378-380, IEEE, 2019. [doi]

@inproceedings{HaLLMJHCPSPKLPC19,
  title = {A 7.5Gb/s/pin LPDDR5 SDRAM With WCK Clocking and Non-Target ODT for High Speed and With DVFS, Internal Data Copy, and Deep-Sleep Mode for Low Power},
  author = {Kyung-Soo Ha and Chang-Kyo Lee and Dongkeon Lee and Daesik Moon and Jin-Hun Jang and Hyong-Ryol Hwang and Hyung-Joon Chi and Junghwan Park and Seungjun Shin and Dukha Park and Sang Yun Kim and Sukhyun Lim and Kiwon Park and YeonKyu Choi and Young-Hwa Kim and Younghoon Son and Hyunyoon Cho and Byongwook Na and Hyo-Joo Ahn and SeungSeob Lee and Seouk-Kyu Choi and Youn-Sik Park and Seok-Hun Hyun and Soobong Chang and Hyuck-Joon Kwon and Jung Hwan Choi and Tae-young Oh and Young-Soo Sohn and Kwang-Il Park and Seong-Jin Jang},
  year = {2019},
  doi = {10.1109/ISSCC.2019.8662509},
  url = {https://doi.org/10.1109/ISSCC.2019.8662509},
  researchr = {https://researchr.org/publication/HaLLMJHCPSPKLPC19},
  cites = {0},
  citedby = {0},
  pages = {378-380},
  booktitle = {IEEE International Solid- State Circuits Conference, ISSCC 2019, San Francisco, CA, USA, February 17-21, 2019},
  publisher = {IEEE},
  isbn = {978-1-5386-8531-0},
}