Modeling and analyzing timing faults in transaction level SystemC programs

Reza Hajisheykhi, Ali Ebnenasir, Sandeep S. Kulkarni. Modeling and analyzing timing faults in transaction level SystemC programs. In Maurizio Palesi, Terrence S. T. Mak, Masoud Daneshtalab, editors, Network on Chip Architectures, NoCArc '13, in conjunction with the 46th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO-46, Davis, CA, USA, December 7, 2013. pages 65-68, ACM, 2013. [doi]

Abstract

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