Modeling and analysis of path delay faults in VLSI circuits: a statistical approach

Mustapha Hamad. Modeling and analysis of path delay faults in VLSI circuits: a statistical approach. In Proceedings of the 2003 10th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2003, Sharjah, United Arab Emirates, December 14-17, 2003. pages 587-590, IEEE, 2003. [doi]

Abstract

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