Design Verification of a Microprocessor Using Branching Time Regular Temporal Logic

Kiyoharu Hamaguchi, Hiromi Hiraishi, Shuzo Yajima. Design Verification of a Microprocessor Using Branching Time Regular Temporal Logic. In Gregor von Bochmann, David K. Probst, editors, Computer Aided Verification, Fourth International Workshop, CAV 92, Montreal, Canada, June 29 - July 1, 1992, Proceedings. Volume 663 of Lecture Notes in Computer Science, pages 206-219, Springer, 1992.

Abstract

Abstract is missing.