Ke Han, Daokun Li. Low-Latency FPGA Design and Implementation of Hermitian Matrix Inversion Based on Partitioned Systolic Array for Massive MIMO. In 2022 IEEE International Conference on Integrated Circuits, Technologies and Applications, ICTA 2022, Xi'an, China, October 28-30, 2022. pages 15-16, IEEE, 2022. [doi]
Abstract is missing.