A 17.28-Gb/s Transceiver With Hybrid Phase-Interpolated Clock and Data Recovery in 40-nm CMOS

Shuo Han, Sheng-You Liu, Kai-Hung Chou, Min-Shu Shih, Ping-Heng Wu, Ching-Yuan Yang. A 17.28-Gb/s Transceiver With Hybrid Phase-Interpolated Clock and Data Recovery in 40-nm CMOS. In IEEE International Symposium on Circuits and Systems, ISCAS 2026, Shanghai, China, May 24-28, 2026. pages 100-104, IEEE, 2026. [doi]

@inproceedings{HanLCSWY26,
  title = {A 17.28-Gb/s Transceiver With Hybrid Phase-Interpolated Clock and Data Recovery in 40-nm CMOS},
  author = {Shuo Han and Sheng-You Liu and Kai-Hung Chou and Min-Shu Shih and Ping-Heng Wu and Ching-Yuan Yang},
  year = {2026},
  doi = {10.1109/ISCAS66217.2026.11562809},
  url = {https://doi.org/10.1109/ISCAS66217.2026.11562809},
  researchr = {https://researchr.org/publication/HanLCSWY26},
  cites = {0},
  citedby = {0},
  pages = {100-104},
  booktitle = {IEEE International Symposium on Circuits and Systems, ISCAS 2026, Shanghai, China, May 24-28, 2026},
  publisher = {IEEE},
  isbn = {979-8-3315-7769-8},
}