A novel high performance low power CMOS NOR gate using Voltage Scaling and MTCMOS technique - researchr publication

researchr

You are not signed in
Sign in
Sign up

Ankish Handa, Jitesh Chawla, Geetanjali Sharma. A novel high performance low power CMOS NOR gate using Voltage Scaling and MTCMOS technique. In 2014 International Conference on Advances in Computing, Communications and Informatics, ICACCI 2014, Delhi, India, September 24-27, 2014. pages 624-629, IEEE, 2014. [doi]

Abstract is missing.

runs on WebDSL