A Computer Architecture for High Pin Count Testers

Christopher J. Hannaford. A Computer Architecture for High Pin Count Testers. In Proceedings IEEE International Test Conference 1991, Test: Faster, Better, Sooner, Nashville, TN, USA, October 26-30, 1991. pages 1042-1048, IEEE Computer Society, 1991.

@inproceedings{Hannaford91,
  title = {A Computer Architecture for High Pin Count Testers},
  author = {Christopher J. Hannaford},
  year = {1991},
  tags = {architecture},
  researchr = {https://researchr.org/publication/Hannaford91},
  cites = {0},
  citedby = {0},
  pages = {1042-1048},
  booktitle = {Proceedings IEEE International Test Conference 1991, Test: Faster, Better, Sooner, Nashville, TN, USA, October 26-30, 1991},
  publisher = {IEEE Computer Society},
  isbn = {0-8186-9156-5},
}