Mohammad Shihabul Haque, Akash Kumar, Yajun Ha, Qiang Wu, Shaobo Luo. TRISHUL: A single-pass optimal two-level inclusive data cache hierarchy selection process for real-time MPSoCs. In 18th Asia and South Pacific Design Automation Conference, ASP-DAC 2013, Yokohama, Japan, January 22-25, 2013. pages 320-325, IEEE, 2013. [doi]
@inproceedings{HaqueKHWL13,
title = {TRISHUL: A single-pass optimal two-level inclusive data cache hierarchy selection process for real-time MPSoCs},
author = {Mohammad Shihabul Haque and Akash Kumar and Yajun Ha and Qiang Wu and Shaobo Luo},
year = {2013},
doi = {10.1109/ASPDAC.2013.6509615},
url = {http://dx.doi.org/10.1109/ASPDAC.2013.6509615},
researchr = {https://researchr.org/publication/HaqueKHWL13},
cites = {0},
citedby = {0},
pages = {320-325},
booktitle = {18th Asia and South Pacific Design Automation Conference, ASP-DAC 2013, Yokohama, Japan, January 22-25, 2013},
publisher = {IEEE},
isbn = {978-1-4673-3029-9},
}