Shintaro Harada, Xu Bai, Michitaka Kameyama, Yoshichika Fujioka. Design of a Logic-in-Memory Multiple-Valued Reconfigurable VLSI Based on a Bit-Serial Packet Data Transfer Scheme. In IEEE 44th International Symposium on Multiple-Valued Logic, ISMVL 2014, Bremen, Germany, May 19-21, 2014. pages 214-219, IEEE, 2014. [doi]
Abstract is missing.