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Static probabilistic worst case execution time estimation for architectures with faulty instruction caches

Damien Hardy, Isabelle Puaut. Static probabilistic worst case execution time estimation for architectures with faulty instruction caches. In Michel Auguin, Robert de Simone, Robert Davis, Emmanuel Grolleau, editors, 21st International Conference on Real-Time Networks and Systems, RTNS 2013, Sophia Antipolis, France, October 17-18, 2013. pages 35-44, ACM, 2013. [doi]

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