Reduction of Power Dissipation in Dynamic BiCMOS Logic Gates by Transistor Reordering

S. M. Rezaul Hasan, Yufridin Wahab. Reduction of Power Dissipation in Dynamic BiCMOS Logic Gates by Transistor Reordering. VLSI Design, 2002(2):547-553, 2002. [doi]

Abstract

Abstract is missing.