Seyedeh Hanieh Hashemi, Reza Namazian, Zainalabedin Navabi. Optimistic clock adjustment for preventing Better-than-worst-case violations. In 2016 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016, Tallinn, Estonia, September 26-28, 2016. pages 1-6, IEEE, 2016. [doi]
@inproceedings{HashemiNN16,
title = {Optimistic clock adjustment for preventing Better-than-worst-case violations},
author = {Seyedeh Hanieh Hashemi and Reza Namazian and Zainalabedin Navabi},
year = {2016},
doi = {10.1109/VLSI-SoC.2016.7753571},
url = {http://dx.doi.org/10.1109/VLSI-SoC.2016.7753571},
researchr = {https://researchr.org/publication/HashemiNN16},
cites = {0},
citedby = {0},
pages = {1-6},
booktitle = {2016 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016, Tallinn, Estonia, September 26-28, 2016},
publisher = {IEEE},
isbn = {978-1-5090-3561-8},
}