Takushi Hashida, Yasumoto Tomita, Yuuki Ogata, Kosuke Suzuki, Shigeto Suzuki, Takanori Nakao, Yuji Terao, Satofumi Honda, Sota Sakabayashi, Ryuichi Nishiyama, Akihiko Konmoto, Yoshitomo Ozeki, Hiroyuki Adachi, Hisakatsu Yamaguchi, Yoichi Koyanagi, Hirotaka Tamura. A 36 Gbps 16.9 mW/Gbps transceiver in 20-nm CMOS with 1-tap DFE and quarter-rate clock distribution. In Symposium on VLSI Circuits, VLSIC 2014, Digest of Technical Papers, Honolulu, HI, USA, June 10-13, 2014. pages 1-2, IEEE, 2014. [doi]
@inproceedings{HashidaTOSSNTHS14,
title = {A 36 Gbps 16.9 mW/Gbps transceiver in 20-nm CMOS with 1-tap DFE and quarter-rate clock distribution},
author = {Takushi Hashida and Yasumoto Tomita and Yuuki Ogata and Kosuke Suzuki and Shigeto Suzuki and Takanori Nakao and Yuji Terao and Satofumi Honda and Sota Sakabayashi and Ryuichi Nishiyama and Akihiko Konmoto and Yoshitomo Ozeki and Hiroyuki Adachi and Hisakatsu Yamaguchi and Yoichi Koyanagi and Hirotaka Tamura},
year = {2014},
doi = {10.1109/VLSIC.2014.6858359},
url = {http://dx.doi.org/10.1109/VLSIC.2014.6858359},
researchr = {https://researchr.org/publication/HashidaTOSSNTHS14},
cites = {0},
citedby = {0},
pages = {1-2},
booktitle = {Symposium on VLSI Circuits, VLSIC 2014, Digest of Technical Papers, Honolulu, HI, USA, June 10-13, 2014},
publisher = {IEEE},
isbn = {978-1-4799-3327-3},
}