33.3 Via-Switch FPGA: 65nm CMOS Implementation and Architecture Extension for Al Applications

Masanori Hashimoto, Xu Bai, Naoki Banno, Munehiro Tada, Toshitsugu Sakamoto, Jaehoon Yu, Ryutaro Doi, Yusuke Araki, Hidetoshi Onodera, Takashi Imagawa, Hiroyuki Ochi, Kazutoshi Wakabayashi, Yukio Mitsuyama, Tadahiko Sugibayashi. 33.3 Via-Switch FPGA: 65nm CMOS Implementation and Architecture Extension for Al Applications. In 2020 IEEE International Solid- State Circuits Conference, ISSCC 2020, San Francisco, CA, USA, February 16-20, 2020. pages 502-504, IEEE, 2020. [doi]

Authors

Masanori Hashimoto

This author has not been identified. Look up 'Masanori Hashimoto' in Google

Xu Bai

This author has not been identified. Look up 'Xu Bai' in Google

Naoki Banno

This author has not been identified. Look up 'Naoki Banno' in Google

Munehiro Tada

This author has not been identified. Look up 'Munehiro Tada' in Google

Toshitsugu Sakamoto

This author has not been identified. Look up 'Toshitsugu Sakamoto' in Google

Jaehoon Yu

This author has not been identified. Look up 'Jaehoon Yu' in Google

Ryutaro Doi

This author has not been identified. Look up 'Ryutaro Doi' in Google

Yusuke Araki

This author has not been identified. Look up 'Yusuke Araki' in Google

Hidetoshi Onodera

This author has not been identified. Look up 'Hidetoshi Onodera' in Google

Takashi Imagawa

This author has not been identified. Look up 'Takashi Imagawa' in Google

Hiroyuki Ochi

This author has not been identified. Look up 'Hiroyuki Ochi' in Google

Kazutoshi Wakabayashi

This author has not been identified. Look up 'Kazutoshi Wakabayashi' in Google

Yukio Mitsuyama

This author has not been identified. Look up 'Yukio Mitsuyama' in Google

Tadahiko Sugibayashi

This author has not been identified. Look up 'Tadahiko Sugibayashi' in Google