A power optimization method considering glitch reduction by gate sizing - researchr publication authors

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Masanori Hashimoto, Hidetoshi Onodera, Keikichi Tamaru. A power optimization method considering glitch reduction by gate sizing. In Anantha Chandrakasan, Sayfe Kiaei, editors, Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998, Monterey, California, USA, August 10-12, 1998. pages 221-226, ACM, 1998. [doi]

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