An Efficient Constant Multiplier Architecture Based on Vertical-Horizontal Binary Common Sub-expression Elimination Algorithm for Reconfigurable FIR Filter Synthesis - researchr publication

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Indranil Hatai, Indrajit Chakrabarti, Swapna Banerjee. An Efficient Constant Multiplier Architecture Based on Vertical-Horizontal Binary Common Sub-expression Elimination Algorithm for Reconfigurable FIR Filter Synthesis. IEEE Trans. on Circuits and Systems, 62-I(4):1071-1080, 2015. [doi]

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